The present invention relates to a nonvolatile memory. In particular, the present invention relates to a ferroelectric memory that can act both as a volatile memory and as a nonvolatile memory.
A ferroelectric memory is a memory simultaneously realizing random access and nonvolatile storing by integrating a semiconductor device and a ferroelectric capacitor. Moreover, because the structure and operation principle of the ferroelectric memory are similar to those of a DRAM (dynamic random access memory), it is considered that an integration degree and an operation speed almost equal to those of the DRAM can be realized.
The ferroelectric memory stores information in the direction of remanent polarization of the ferroelectric capacitor. Therefore, the ferroelectric capacitor has a problem of fatigue. The magnitude of the remanent polarization of the ferroelectric capacitor decreases after repeating polarization reversal 10.sup.10 to 10.sup.12 times. Due thereto, the intensity of the signal for reading information is decreased and it is difficult to stably operate the memory. Therefore, the life of the ferroelectric memory is limited by the polarization reversal frequency of the ferroelectric capacitor.
The degree of the fatigue depends on the materials of the ferroelectric film and of the electrodes. For example, as shown in the Japanese Journal of Applied Physics, Vol. 34 (1995) pp. 5233-5239, the value of remanent polarization of a ferroelectric film made of PZT (lead zirconate-titanate) is larger than that of a ferroelectric film made of SrBi.sub.2 Ta.sub.2 O.sub.9, but the fatigue of the latter is smaller than that of the former. For example, as shown in Integrated Ferroelectrics, Vol. 3 (1993), pp. 365-376, the fatigue of an electrode made of ruthenium oxide is smaller than that of an electrode made of Pt even when the ferroelectric film is made of PZT.
To solve the problem of the shortening of the life due to fatigue, a ferroelectric memory called a shadow RAM has been proposed so far. The shadow RAM stores positive or negative electric charges (volatile information) accumulated in a capacitor in normal operation similarly to a DRAM and simultaneously converts the information into the polarization direction (nonvolatile information) when turning off the power supply (store operation). When turning on the power supply, the shadow RAM converts the nonvolatile information into volatile information (recall operation). Because it is possible to read or write the volatile information without causing polarization reversal, this method makes it possible to decrease the polarization reversal frequency of the ferroelectric capacitor and prolong the life.
Conventional example 1 of a shadow RAM is disclosed in Japanese Patent Laid-Open No. 283176/1991. FIG. 21(a) of the present application shows a memory cell of this shadow RAM. The shadow RAM is constituted by arranging a plurality of such memory cells in an array. One electrode PL of a ferroelectric capacitor C is connected in common with the ferroelectric capacitors of other memory cells. The other electrode SN of C is connected with the source electrode of a MOS transistor MN. The drain of MN is connected to a data line DL. The gate electrode of MN is connected to a word line WL.
In the volatile mode, PL is set to Vss. To write information, WL is set to Vch, MN is turned on, DL is set to Vcc or Vss in accordance with whether the information to be stored is "0" or "1", and, thereby, WL is lowered to Vss to accumulate electric charge in C. In this case, Vss denotes a ground potential, Vcc denotes a power supply potential, and Vch denotes a potential higher than Vcc. To read information, DL is pre-charged to Vcc/2, and thereafter WL is raised up to Vch to detect the polarity of the electric charge flowing into the data line, from the capacitor, by a sense amplifier.
These states are shown by the hysteresis curve showing the state of a ferroelectric capacitor in FIG. 21(b). The potential of SN is V(SN) and that of PL is V(PL). The graph shows the voltage V(SN)-V(PL) applied to the ferroelectric capacitor as the abscissa, and the electric charge Q, which is a value obtained by multiplying the polarization of the capacitor by the area of the capacitor, as the ordinate. To reverse the polarization of the ferroelectric capacitor, defining the minimum voltage to be applied to both ends of the capacitor as the coercive voltage Vc, the circuit is designed so that Vc is smaller than Vcc/2. Because PL is set to Vss, the value Q is D1 when "1" of the volatile information is stored and Do when "0" of the volatile information is stored. The polarization is not reversed because only a positive voltage is applied to the capacitor during volatile operation.
In the nonvolatile mode, PL is set to Vcc/2. To write information, WL is raised to Vch and DL is set to Vcc or Vss in accordance with "1" or "0" of information to be stored. The states on the hysteresis curve at this stage are located at B1 and B0. Finally, DL is returned to Vcc/2 and then WL is lowered to Vss. The state of the capacitor changes from B1 to F1 or from B0 to F0. That is, in the nonvolatile mode, polarization reversal occurs because a positive or negative voltage is applied to the capacitor. To read the direction of polarization, DL is pre-charged to Vss and WL is raised up to Vch to detect presence or absence of a polarization reversal current by a sense amplifier. Therefore, polarization is reversed even at the time of read.
Conventional example 2 of a shadow RAM, which is disclosed in Japanese Patent Laid-Open No. 5996/1991, will be described in the following. FIG. 22(a) shows a memory cell of this shadow RAM and FIG. 22(b) shows the state on a hysteresis loop. In this example, design is so made as to meet Vcc/2&lt;Vc&lt;Vcc.
In the volatile mode, PL is set to Vcc/2. To write information, WL is set to Vch to turn on MN, DL is set to Vcc or Vss and thereby WL is lowered to Vss to accumulate electric charge in C. Because PL is Vcc/2 on the hysteresis curve, the state is located at the position D1 when volatile information "1" is stored, and at the position D0 when volatile information "0" is stored. Though a positive or negative voltage is applied to the capacitor during write or read operation, polarization is not reversed theoretically because Vc is higher than Vcc/2. However, a small polarization reversal normally occurs as shown in FIG. 22(b).
In the nonvolatile mode, information is written by driving PL. DL is set to Vcc or Vss in accordance with "1" or "0" of the information to be written, and then WL is raised up to Vch. Then, PL is raised from Vss up to Vcc and returned to Vss again to cause polarization reversal. Finally, DL is returned to Vss and thereafter WL is lowered to Vss. By this operation, the state shifts to F1 after passing B1 and shifts to F0 after passing B0 on the hysteresis curve. That is, because a sufficiently high positive or negative voltage is applied to the capacitor by driving PL, polarization reversal occurs. To read information, PL is lowered to Vss, DL is precharged up to Vcc, and WL is raised up to Vch to detect the presence or absence of a polarization reversal current by a sense amplifier. Therefore, polarization is reversed also to read information.
Finally, conventional example 3 of a RAM whose operation is similar to a shadow RAM, disclosed in Japanese Patent Laid-Open No. 21784/1995, will be described below. FIG. 23(a) shows a memory cell of this RAM and FIG. 23(b) shows the state of a hysteresis loop. In this example, design is so made as to meet Vc&lt;Vcc/2.
In this example, PL is set to Vcc/2 both in the volatile and nonvolatile modes. To write volatile information, WL is set to Vch to turn on MN, DL is set to Vcc or Vss, and, then, WL is lowered to Vss to accumulate electric charge in C. Because PL is Vcc/2 on the hysteresis curve, the state is located at the position D1 when volatile information "1" is stored and at the position of D0 when volatile information "0" is stored. Because a positive or negative voltage is applied to the capacitor and the critical voltage Vc is lower than Vcc/2, polarization reversal occurs. That is, volatile write simultaneously causes nonvolatile write and the polarity of electric charge always corresponds to the direction of polarization. At the time of volatile read, only electric charge is read. DL is pre-charged up to Vcc/2, and, thereafter, WL is raised up to Vch to detect the polarity of the electric charge flowing into a data line from the capacitor. Therefore, polarization reversal does not occur at the time of read.
In the nonvolatile mode, polarization is read. DL is precharged up to Vss, and, thereafter, WL is raised up to Vch to detect the presence or absence of a polarization reversal current by a sense amplifier. Therefore, the polarization is reversed at the time of nonvolatile read.
In the case of conventional example 1, the potential of plate electrode PL is changed for volatile operation and nonvolatile operation. Therefore, it is necessary to change the plate potential during the store operation when turning off the power supply. PL is first set to Vss when reading the volatile information and it is raised up to Vcc/2 after sensing a signal to write the volatile information as nonvolatile information. This store operation is simultaneously performed for memory cells connected to one word line. Therefore, to perform a store operation for all memory cells, it is necessary to select all word lines in order and repeat the operation for changing the plate potential each time. Also for the recall operation, the same PL control is necessary. PL has a large parasitic capacitance because it is common to all memory cells. Therefore, it is difficult to perform the store operation and the recall operation at a high speed, and, moreover, power consumption increases.
In conventional example 2 PL is pulse-driven during the nonvolatile operation. Therefore, because PL is divided in the word-line direction, this brings about a problem that the area of the memory cell increases. Moreover, it is difficult to increase the operating speed because it is necessary to time the driving of PL, though the parasitic capacitance of PL is smaller than that of conventional example 1.
Therefore, the method of changing the volatile operation mode and the nonvolatile operation mode by the plate potential or its driving method has problems that the chip area increases, the store or recall operation speed decreases, and the power consumption increases. In the case of conventional example 3, these problems are solved by setting PL to Vcc/2 for both nonvolatile operation and volatile operation. However, conventional example 3 has a problem that the write frequency is limited because polarization reversal occurs during volatile write. A problem to be solved by the present invention is to realize a shadow RAM causing no polarization reversal during volatile operation without changing the potential of the plate electrode PL during volatile and nonvolatile operations.
In the case of conventional examples 1 and 2, because the store operation is complex, it is difficult to completely perform the store operation when the power supply is suddenly turned off due to a problem in the system in which a ferroelectric memory is installed. Therefore, in the case of conventional examples 1 and 2, information may be lost when the power supply is turned off without performing the store operation, because remanent polarization is uniformly directed in a certain direction and no nonvolatile information is stored. However, conventional example 3 realizes one method for solving the above problem because volatile information and nonvolatile information are written at the same time, and, therefore, the information when the power supply is turned off without performing the store operation remains as nonvolatile information. Another problem to be solved by the present invention is to store nonvolatile information independently of volatile information by reading or writing volatile information without changing nonvolatile information.
A third problem to be solved by the present invention is to effectively use to advantage the fact that even a capacitor using PZT for a ferroelectric film and Pt for an electrode has a large remanent polarization by improving the operation method and reducing the fatigue.